1. Technical Field
The present invention pertains to memory devices. In particular, the present invention pertains to a data bus structure for a dynamic random access memory (DRAM) that includes a series of data buses, each shared by a plurality of memory banks, and a switching device to selectively couple the data buses to a global data bus to enable the memory device to provide and receive data. The data bus structure conserves space on a chip or die and prevents significant timing skews for data accessed from different memory banks.
2. Discussion of the Related Art
Memory devices are utilized to store information for various applications. A commonly utilized memory device includes a dynamic random access memory (DRAM). These types of memory devices store information in memory cell arrays that are configured in a matrix of intersecting rows and columns. The rows are commonly referred to as word lines. Each memory cell generally includes a storage capacitor to hold a charge and a transistor to access the charge of the capacitor. The charge may be a high or low voltage potential (referred to as a data bit), thereby providing the memory cell with two logic states.
There are several forms of DRAM devices. For example, a double data rate (DDR) memory device provides increased performance and basically enables output operations to be performed on both the rising and falling edges of a clock signal. This effectively increases the clock frequency without actual alteration of the clock signal. A conventional DDR type DRAM device is illustrated in FIG. 1. Specifically, a memory device 10 is in the form of a chip or die and includes a plurality of cell arrays or memory banks 12a-12h each including a series of sub memory cell arrays 15 and corresponding sense amplifiers 16. The chip or die is typically substantially rectangular with the memory banks arranged in two rows of four banks with each row disposed along a respective longer dimensioned edge of the chip (e.g., memory banks 12a, 12b, 12e and 12f are disposed toward an upper chip edge and memory banks 12c, 12d, 12g and 12h are disposed toward a lower chip edge as viewed in FIG. 1). The memory device provides a storage capacity of one gigabit distributed evenly among memory banks 12a-12h (e.g., each memory bank includes a storage capacity of approximately one-hundred twenty-eight megabits).
Each memory bank is associated with a row decoder 14, a column decoder 18, a local data bus 20, secondary sense amplifiers 22, a write driver 23 and a bank data bus 24 (e.g., RWD0-RWD7 as viewed in FIG. 1). A column decoder and control area 21 is disposed below each memory bank 12a-12h and includes column decoder and control circuitry (e.g., column decoder 18, local data bus 20, secondary sense amplifiers 22, write driver 23, bank data bus 24, etc.) for that memory bank. The row decoders for two adjacent memory banks within a row are disposed next to each other along corresponding memory bank side edges. Thus, row decoders 14 of memory banks 12a, 12b are disposed next to each other between side edges of those memory banks, while the row decoders of memory banks 12e, 12f are similarly disposed next to each other and between side edges of those memory banks. The row decoders for adjacent memory banks 12c, 12d and 12g, 12h within the lower row are arranged in a similar fashion.
The row decoder enables a row (or word) within a corresponding memory bank in accordance with a provided memory address, while sense amplifiers 16 enable transference of information with individual memory cells. The column decoder selects corresponding sense amplifiers or columns for accessing particular memory cells in accordance with the provided address. Local data bus 20 transfers information between sense amplifiers 16 and secondary sense amplifiers 22 and write driver 23. The secondary sense amplifiers amplify the signals selected by the column decoder to drive bank data bus 24 during a read operation, while write driver 23 receives information from bank data bus 24 for a write operation as described below. Each bank data bus 24 is sixty-four bits wide and includes approximately the same length to extend through a corresponding column decoder and control area 21.
The memory device further includes a data peripheral circuit area 28 and an address/command peripheral circuit area 30. The data peripheral circuit area is disposed between the upper and lower rows of memory banks and extends from the chip side edge adjacent memory banks 12a, 12c to the approximate center of the chip. Data peripheral circuit area 28 typically includes a series of pads 34 arranged in two rows (e.g., DQ pads with an upper row disposed below memory bank 12b and a lower row disposed above memory bank 12d) to receive data into and provide data from the memory device, and inputs to receive a strobe (e.g., DQS) for double data rate operation and a data mask (e.g., DM) to selectively block write operations. Data peripheral circuit area 28 may further include circuitry to accommodate and/or process data to and from the memory device.
The address/command peripheral circuit area is disposed between the upper and lower rows of memory banks and extends from the chip side edge adjacent memory banks 12f, 12h to the approximate center of the chip. The address/command peripheral circuit area includes pads 36 arranged in two rows (e.g., ADD/CMD pads with an upper row disposed below memory bank 12e and a lower row disposed above memory bank 12g) to receive and provide address and commands for the memory device, and circuitry to process the address and commands.
In order to transfer data between the memory banks and pads 34, the memory device includes a global data bus 32 (e.g., SRWD as viewed in FIG. 1) coupled to pads 34. The global data bus is partially disposed in both peripheral circuit areas 28 and 30 (e.g., extends in the area between the upper and lower rows of pads 34 and 36 of respective areas 28, 30) and is sixty-four bits wide. The global data bus is further coupled to each bank data bus 24 via multiplexers 26, 27. Multiplexer 26 is coupled to the bank data buses associated with memory banks 12a-12d and is disposed in data peripheral circuit area 28 substantially coincident the adjacent row decoders for those memory banks. Multiplexer 27 is coupled to the bank data buses associated with memory banks 12e-12h and is disposed in address/command peripheral circuit area 30 substantially coincident the adjacent row decoders for those memory banks. Thus, each multiplexer may selectively couple one of four memory banks to the global data bus. Multiplexers 26, 27 selectively couple a bank data bus to global data bus 32 based on a memory address indicating the memory bank containing the desired memory cells for retrieval or storage of information. This enables information to be read from and written to the memory cells of memory banks 12a-12h. 
The memory device provides a plurality of operations to access data. These operations include read and write operations to respectively retrieve and store data in specific memory cells. In order to read from or write to memory cells, the particular cells are selected or addressed. In addition, control information is received from a controller (e.g., a CPU, etc.) to indicate the type of operation (e.g., a write operation or a read operation) to be performed. With respect to a read operation, a row of memory cells in a particular memory bank is enabled by a row decoder 14 based on a provided memory address. The charges of the enabled memory cells are provided to corresponding sense amplifiers 16 that amplify the signals. Column decoder 18 selects the sense amplifiers associated with the desired memory cells based on the provided address, where the selected signals are placed on local data bus 20 for transference to secondary sense amplifiers 22. The secondary sense amplifiers amplify the received signals to place those signals on a corresponding bank data bus 24. The bank data bus is coupled to global data bus 32 via multiplexer 26 or 27 (e.g., depending upon the particular memory bank accessed as described above) for transference of the signals to pads 34. The pads enable peripheral circuitry to provide the signals as output from the memory device.
A write operation places data received by pads 34 (e.g., from peripheral circuitry receiving data from an external source) into desired memory cells. The data from pads 34 is placed on global bus 32 and transferred to a data bus 24 associated with the memory bank containing the desired memory cells via multiplexer 26 or 27 (e.g., depending upon the memory bank accessed). Write driver 23 transfers the data from data bus 24 to local data bus 20 for conveyance to sense amplifiers 16. The sense amplifiers store the data in the desired memory cells of the associated memory bank in conjunction with the row and column decoders.
The memory device described above suffers from several disadvantages. In particular, the architecture based on eight memory banks usually has a larger die size overhead than four bank architectures since the global data bus extends into the address/command peripheral circuit area. Further, the architecture described above employs two multiplexers to couple bank data buses to the global data bus (and pads). One multiplexer is disposed in the data peripheral circuit area adjacent the pads, while the other multiplexer is disposed in the address/command peripheral circuit area as described above. However, the distance for data to travel over the global data bus from the multiplexer disposed in the data peripheral circuit area to the pads is shorter than the distance for data to travel from the other multiplexer to those pads. This results in a significant or large data timing skew on the global data bus. In other words, the travel time for data from the respective multiplexers (and corresponding memory banks) varies. In addition, the architecture described above employs two multiplexers, thereby complicating signal routing in the peripheral circuit areas.